Exemplary embodiments of the present invention relate to a fabrication technology of a semiconductor device, and more particularly, to a semiconductor device including an isolation layer, and a method for fabricating the same.
A semiconductor device includes a plurality of structures, for example, transistors. The respective transistors have different operating voltages. That is, the semiconductor device is fabricated by integrating a plurality of high-voltage transistors and a plurality of low-voltage transistors into a single chip or die.
Meanwhile, the semiconductor device requires isolation layers which electrically isolate the transistors having different operating voltages. The isolation layers have different shapes, that is, critical dimensions and/or depths, according to the operating voltages of the transistors. In general, the isolation layers which isolate the plurality of high-voltage transistors from one another have critical dimensions and depths larger than those of the isolation layers which isolate the plurality of low-voltage transistors.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
Referring to FIG. 1A, a substrate 11 has a high-voltage region in which a high-voltage transistor is to be formed, and a low-voltage region in which a low-voltage transistor is to be formed. The low-voltage transistor is a transistor which has an operating voltage lower than that of the high-voltage transistor. A first well 12 and a second well 13 are formed by implanting impurity ions into the low-voltage region and the high-voltage region of the substrate 11, respectively.
A hard mask pattern 14 is formed on the substrate 11, and a plurality of trenches are formed in the high-voltage region and the low-voltage region by etching the substrate 11 using the hard mask pattern 14 as an etch barrier. Hereinafter, the trench formed in the low-voltage region will be referred to as a first trench 15, and the trench formed in the high-voltage region will be described as a second trench 16.
Referring to FIG. 1B, a sacrificial pattern 17 is formed to cover the high-voltage region and expose the low-voltage region. An insulation layer 18 is deposited over the substrate 11 to fill the first trench 15.
Referring to FIG. 1C, a first isolation layer 18A is formed in the low-voltage region by performing a planarization process until the top surface of the hard mask pattern 14 is exposed. The sacrificial pattern 17 is removed to expose the trench of the high-voltage region, that is, the second trench 16.
The bottom surface of the second trench 16 of the high-voltage region is additionally etched using the hard mask pattern 14 as an etch barrier to thereby increase the depth of the second trench 16. Hereinafter, the second trench 16 whose depth is increased will be represented by reference numeral “16A”.
Referring to FIG. 1D, an insulation layer 19 is deposited over the substrate 11 to completely fill the second trench 16A.
In order to eliminate the height difference of the insulation layer 19 which is caused by the first isolation layer 18A having been formed in the low-voltage region, a photoresist pattern 20 is formed to cover the high-voltage region. The height difference of the insulation layer 19 between the high-voltage region and the low-voltage region is reduced by partially etching the insulation layer 19 formed in the low-voltage region. The photoresist pattern 20 is then removed.
Referring to FIG. 1E, a second isolation layer 19A is formed in the high-voltage region by performing a planarization process until the top surface of the hard mask pattern 14 is exposed, and the hard mask pattern 14 is removed.
The semiconductor device fabricated through the above-described processes has a structure in which the first isolation layer 18A is disposed at one side of a boundary region, in which the first well 12 and the second well 13 are in contact with each other, and the second isolation layer 19A is disposed at the other side thereof. Thus, stress is concentrated in the boundary region in which the first well 12 and the second well 13 are in contact with each other (see reference symbol “A” of FIG. 1E). In particular, since the gap between the boundary regions in which the first and second isolation layers 18A and 19A and the first and second wells 12 and 13 are in contact with one another is narrow, stress is further concentrated. The concentration of stress degrades the characteristics of the semiconductor device which will be fabricated in the first and second wells 12 and 13 through subsequent processes.
Furthermore, since the first well 12 and the second well 13 are in contact with each other between the first and second isolation layers 18A and 19A, the inter-well breakdown voltage characteristic and leakage current characteristic are degraded by the difference of the operating voltage between the high-voltage region and the low-voltage region. In order to improve the inter-well breakdown voltage characteristic and leakage current characteristic, the gap between the first and second isolation layers 18A and 19A adjacent to the boundary region in which the first and second wells 12 and 13 are in contact with each other must be increased. However, if the gap between the first and second isolation layers 18A and 19A is increased, the integration density of the semiconductor device is lowered.
Moreover, since the surfaces of the first well 12 and the second well 13 in their contact region are in the exposed state, an inter-well electrical short occurs when a silicide process is performed. Consequently, an additional process for substantially preventing the inter-well electrical short is required.